Short Biography

Professor Yannis Papaefstathiou

Technical University of Crete, Greece

Tutorial title: "Implementation of Hardware Accelerators for Machine Learning"

Short Biography: Dr. Ioannis Papaefstathiou was granted a PhD degree in computer science from the University of Cambridge UK, in 2000 and he is an Assistant Professor at the ECE Department of the Technical University of Crete since June 2004. Between 2001 and 2005 he was a visiting assistant professor at the University of Crete, Greece and a research associate at ICS-FORTH.

He received his M.Sc. degree from Harvard University, Cambridge, MA, in 1997 and his B.Sc. degree from the University of Crete, Greece in 1996. His current research interests focus on architectures for network processors and specific purpose networking systems. He has participated in a number of multi-national projects and has published more than 30 papers in journals and premier international conferences. He has been a guest editor of a special issue of IEEE Micro.

He has also been a reviewer for a number of international journals such as IEEE Micro, Elsevier Journal on "Microprocessors and Microsystems", ΙΕΕΕ Communication Letters, International Journal of Control, Automation, and Systems and conferences such as 10th IEEE International Symposium on High Performance Computer Architecture (HPCA-10), 2004 International Symposium on Low Power Electronics and Design (ISLPED'04), 30th ΙΕΕΕ International Symposium on Computer Architecture (ISCA'03), ΙΕΕΕ International Conference on VLSI 2003 (VLSI'03). 3rd IEEE Network Processor Workshop (NP3) while he was a member of the programming committe of 10th International Conference on Information Systems Analysis and Synthesis (ISAS 2004).

Research areas: Interested in the architecture and design of novel computer systems, focusing mostly on media and network processing devices and the interaction between VLSI and computer architecture. Currently concentrating on the design and implementation of specific purpose microprocessors with tightly coupled design parameters and highly constrained resources such as network processors. Successful designs in this area require optimization in both hardware and software and they integrate ideas from computer networking with ideas from system design and computer architecture. Also interested in high-speed systems for encryption, compression or any other data manipulation method.

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