Implementation of Hardware Accelerators for Machine Learning

Prof. Yannis Papaefstathiou (Short Biography)

Machine Learning (ML) in general and Deep Learning (DL) in particular have been widely accepted as the most prominent approaches for solving very complex problems in numerous application domains. However, their computational and power demands can be forbiddingly high when executed on General Purpose CPUs. As a result, it is highly desirable to implement such schemes in reconfigurable hardware accelerators.

This tutorial will begin with an overview of the main ML and DL schemes that have been implemented in hardware so far. Then it will focus on how a software developer can utilize High Level Synthesis so as to develop such an efficient accelerator in a modern reconfigurable hardware device (i.e. FPGA);  this will be illustrated in the design of a certain widely used DL module. Furthermore, a number of optimizations, applicable to most ML and DL schemes that allow the designer to explore in full the capabilities of the modern FPGAs will be presented.

Tutorial by Professor John MacIntyre

Prof. John MacIntyre (Short Biography)

A tutorial will be run by Professor John MacIntyre, Pro Vice Chancellor University of Sunderland, UK Editor-in-Chief, Neural Computing & Applicatons Springer Journal Impact factor, and Chair of the National Association of College and University Entrepreneurs (NACUE). More information about the tutorial will be available soon.

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